The present invention relates to an operation of a nonvolatile memory device and, more particularly, to a program method of a nonvolatile memory device, which can prevent collision between a cache program and an intelligent verify method.
Flash memory, i.e., nonvolatile memory is generally classified into NAND flash memory and NOR flash memory. NOR flash memory has a structure in which respective memory cells are connected to bit lines and word lines independently and therefore has an excellent random access time characteristic, whereas NAND flash memory has a structure in which a plurality of memory cells is connected in series and only one contact is required on a per cell-string basis and is therefore excellent in the degree of integration. Thus, the NAND structure is usually used in high-integrated flash memory.
A well-known NAND flash memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array is comprised of a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings, each corresponding to the bit lines.
A flash memory device employs a cache program scheme in order to increase the program speed. The cache program scheme is a method of receiving data to be programmed next time while a program is being performed, storing the received data in a latch of a page buffer, which is not used, and continuously programming the stored data after the program is completed.
If the cache program is performed, the data input speed can be increased since data to be programmed next time is received while a program is being performed. Further, the address input time can also be saved since a block address input when a program command is first issued is used without change and only column address information for a next program is input.
Cache data for the cache program is input to a cache latch of a page buffer. At this time, if cache data is already used before being input, data can be overlapped, resulting in operational error.
That is, if cache data is input to a cache latch while an operation such as an intelligent verify operation is being executed, data stored in the cache latch can be overlapped.
The intelligent verify operation is one of methods for programming data into a flash memory device and verifying the data. According to this method, if the entire bits are not passed and a preset number of fails occurs, a corresponding program is determined as program pass. In the intelligent verify method, fail bits can be modified through error correction, etc.
In general, when the intelligent verify method is performed, data of a main latch is transferred to a cache latch and a verify operation using the cache latch is performed.
Accordingly, while the intelligent verify method is being performed, data of the main latch is stored in the cache latch. At this time, if cache data for a cache program is input, the cache data can be input to the cache latch overlappingly with the stored data.